The present invention relates to a defect inspection apparatus and system to be used in manufacture processes of an electronic device such as a semiconductor integrated circuit, and to a defect inspection program to be executed in the defect inspection apparatus and system.
Related art will be described by taking manufacture of a semiconductor integrated circuit as an example. Processes of manufacturing a semiconductor integrated circuit are generally classified into a front-end process and a back-end process. In the former process, a plurality of chips (products) with multiple layers such as a circuit pattern are formed on a silicon wafer. In the latter process, the silicon wafer is separated into each chip to complete each product. Most of failures during manufacture occur in the long term front-end process including fine patterning. Improvement on the yield of the front-end process is important for low cost production. The yield of the front-end process is a non-defective product factor, i.e., a ratio of non-defective chips to all chips of a wafer, to be determined by the final electrical inspection of the front-end process.
Failures of the front-end process are mainly classified into operational failures and parametric failures. The functional failure is the failure that a circuit does not operate normally because of breakage or short circuit of a circuit pattern mainly caused by particles or pattern defects (hereinafter collectively called defects) generated during manufacture. The parametric failure is the failure that an operation speed of a transistor does not satisfy the design specification because of fine process variations in worked sizes, oxide film thicknesses and the like.
In order to detect particles and pattern defects which cause the functional failure, a defect inspection tool or apparatus such as a dark-field inspection tool or apparatus and a bright-field inspection tool or apparatus has been used at a front-end manufacture line. Generally, the dark-field inspection tool obliquely applies a laser beam to a wafer from an upper position and detects scattered light of the laser beam. The bright-field inspection tool picks up an image of a circuit pattern on a wafer and compares it with a normal pattern image to detect a difference between the normal pattern and abnormal pattern. Depending upon detectors, there are bright-field inspection tools of an optical type and of an electron beam type.
In general manufacture lines, defect data detected with a defect inspection tool is managed in the following manners to improve the manufacture yield.
(1) As described in JP-A-10-115594 and etc., defect data is managed by using a general quality management approach such as a time sequential change in the number of defects and a correlation between the number of defects and a manufacture yield.
(2) As described in JP-A-2000-223385 and etc., defect data is utilized for the analysis of a defect source by comparing the defect data and electrical test results on the basis of coordinate positions in a wafer plane and calculating an influence degree of defects upon a lowered manufacture yield.
(3) As described in JP-A-10-209230 and etc., defect data is utilized for the analysis of a defect source by analyzing the coordinate distribution of defect data in a wafer plane.
(4) As described U.S. Pat. No. 5,801,965 and etc., defect data is utilized for the analysis of a defect source by selecting several defect data pieces from the defect data and picking up each image of these defect data pieces with an image pickup apparatus called a defect review tool or apparatus.
The above-described analysis of defect data is performed on the assumption that all data detected with the defect inspection tool necessarily pertains to actual defects. However, data output from the defect inspection tool includes data pieces relevant to the electrical failure and many other data pieces irrelevant to the electrical failure called nuisance detection or detection error (also called quasi defects). Detection errors include some color variation of a circuit pattern, projections on a circuit pattern called grains, excessive reflection of light applied to a circuit pattern, a fine change in a line width of a circuit pattern and the like, which are neither actual particles nor pattern defects.
Recent semiconductor integrated circuits are becoming finer and finer and even a fine defect may cause a functional failure. A defect inspection tool is required to detect a fine defect, and often used at the ultimate point of the tool specification. In such a case, detection errors are likely to be output.
Such data which contains detection errors may cause an erroneous determination. For example, in the above-described document (1), even if a time sequential change in the number of defects increases, it may be merely an increase in the number of detection errors and the number of actual defects does not increase. In such a case, managing a time sequential change in the number of defects at a manufacture line is meaningless.
Also in the above-described document (4), even if an image of the data containing detection errors is picked up with a defect review tool, this image does not contain the defect to be dealt with and time is wasted.
A conventional method of removing such detection errors is described in JP-A-5-47887. With this method, it is assumed that defects repetitively detected at the same positions of LSI chips on a wafer are detection errors which are excluded from analysis. However, with this method, it is difficult to remove all detection errors.
It is an object of the present invention to provide a defect inspection apparatus and system and a defect inspection computer program capable of solving the problems associated with prior art.
It is another object of the invention to provide a defect inspection apparatus and system and a defect inspection computer program capable of efficiently and effectively detecting detection errors contained in an output of the defect inspection apparatus to exclude them from inspection data.
The present inventors have checked the occurrence positions of detection errors by using past inspection data.
FIG. 6 shows an example of a distribution of positions in an LSI chip from which a defect inspection apparatus output detection errors. In FIG. 6, data of detection errors detected with a defect inspection apparatus is plotted in a schematic LSI chip circuit layout (drawing information of a circuit pattern) 52. A solid black circle represents each detection error. Rectangular frames B1 to B4 represent circuit blocks 1 to 4. A circuit block is a unit which processes an individual function of LSI, such as an input/output block, an A/D converter block, a memory block and a processor block. Each circuit block is constituted of a collection of small circuit blocks. The minimum unit of the circuit block is generally a combinational circuit or a sequential circuit. It has been found from FIG. 6 that the occurrence positions of detection errors are dependent upon the circuit layout such as a boarder area between circuit blocks (e.g., 71a, 71b and 71c in FIG. 6), a peripheral area of a circuit block (e.g., 72a, 72b and 72c) and an inner area of a particular circuit block (e.g., 73a, 73b, 73c, 74a and 74b). It has also been found from the position distribution in an LSI chip that many detection errors do not exist singularly but they exist adjacent to each other.
The inventors have considered from these findings that detection errors can be selected from an output of a defect inspection apparatus and excluded from defect data by storing a relation between detection errors obtained from past inspection data and a circuit layout (drawing information of a circuit pattern) in a detection error database, comparing data newly output from the defect inspection apparatus with information in the detection error database, and determining the data matching the database information as a detection error.
According to one aspect of the present invention, an inspection data analyzing method of determining a detection error from output data of an inspection apparatus which detects a particle or a pattern defect of an inspected object, includes: an inspection data input step of reading inspection data output from the inspection apparatus, the inspection data containing at least one information piece of coordinate value information and size information of the particle or pattern defect of the inspected object; a drawing data input step of reading drawing data of a product of the inspected object; an information extracting step of extracting information representative of a relation between at least one information piece of coordinated value information and size information of the particle or pattern defect of the inspected object in the inspection data input at the inspection data input step, and the drawing data input at the drawing data input step; and a detection error determining step of comparing the information extracted at the information extracting step with determination criterion information registered beforehand and determining whether each particle or pattern defect of the inspected object in the inspection data is a detection error or not.
According to an embodiment of the invention, the determination criterion information is past inspection data of detection errors.
According to an embodiment of the invention, the determination criterion information is data representative of occurrence positions of past detection errors in a circuit block in the drawing data.
According to an embodiment of the invention, the drawing data to be read is circuit layout data generated by computer-aided design.
According to an embodiment of the invention, the extracted information includes coordinate value information of each particle or pattern defect of the inspected object in the inspection data in a circuit block corresponding to the drawing data.
According to the invention constructed as above, by using the past detection error data and the circuit layout information corresponding to the detection error data, the detection error database is created. It is therefore possible to efficiently find a detection error from inspection data newly output from the defect inspection apparatus. By utilizing the inspection data excluding detection errors for the defect analysis, the manufacture yield of electronic devices typically semiconductor integrated circuits can be improved effectively.
Other objects, features and advantages of the invention will become apparent from the following description of the embodiments of the invention taken in conjunction with the accompanying drawings.